A Priori Wire Length Estimates for Digital Design by Dirk Stroobandt

By Dirk Stroobandt

The roots of this booklet, and of the hot learn box that it defines, lie within the scaling of VLSI expertise. With gigahertz method clocks and ever­ accelerating layout and technique ideas, interconnects became the proscribing issue for either functionality and density. This expanding effect of interconnects at the approach implementation house necessitates new instruments and analytic recommendations to help the process clothier. With recognize to modeling and research, the reaction to interconnect dom­ inance is evolutionary. Atomistic- and grain-level versions of interconnect constitution, and function types at multi-gigahertz working frequencies, jointly advisor the choice of more advantageous fabrics and procedure applied sciences (e. g. , damascene copper wires, low-permittivity dielectrics). formerly in­ major results (e. g. , mutual inductance) are additional into functionality mod­ els, as older approximations (e. g. , lumped-capacitance gate load types) are discarded. even if, on the system-level and chip making plans point, the required reaction to interconnect dominance is progressive. Convergent layout flows don't require merely disbursed RLC line versions, repeater understanding, unifi­ cations with extraction and research, and so on. particularly, matters corresponding to wiring layer project, and early prediction of the source and function envelope for the process interconnect (in specific, in accordance with statistical versions of the procedure interconnect structure), additionally turn into serious. certainly, system-level interconnect prediction has emerged because the enabler of better interconnect modeling, less costly process architectures, and extra efficient layout technology.

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In most partitioning processes, one tries to minimize the number of nets that have to be "cut". 3)2 such that each module can be seen as a new circuit and can be partitioned further in the same way. This kind of recursive partitioning is called a hierarchical partitioning process. The number of possible partitions II for a circuit of G blocks in M modules is very large for any practical case. Assuming that G is divisible by M (B = G / M with B, the number of blocks per module, an integer), the following is valid [ROW71]: IT _ G!

By making the chip smaller, wire lengths are reduced which in turn reduces the signal delay between components of the circuit. At the same time, a smaller area may imply more chips can be produced on a wafer which reduces the manufacturing cost. Naturally, compaction must ensure that no rules regarding the design and fabrication process are violated during the process. This must be checked after each design step. Therefore, the computing time needed for compaction is quite high and this mandates that extensive compaction is used only for large volume applications, such as microprocessors.

From the circuit model above, we deduct that the block degree of a pin always equals 1. In the following, I will only consider the block degree of logic blocks for characterizing the model. Generally we will confine ourselves to the average block degree or the average number of terminals t per logic block. For modelling 'realistic' circuits through the graph model, we need to have a notion of the way in which nets and logic blocks are connected. The most important property of circuits that we want to use, is the interconnection topology.

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